This application claims the benefit of Korean Application No. P2002-55784, filed on Sep. 13, 2002, which is hereby incorporated by reference as if fully set forth herein.
1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a capacitor of a semiconductor device.
2. Discussion of the Related Art
A capacitor of a semiconductor device has been generally made of Oxide-Nitride-Oxide (ONO) dielectric material. However, it is recently required to make a capacitor as a material having high dielectric constant and to manufacture a semiconductor device at a low temperature so as to prevent characteristics of a logic circuit such as a transistor and a capacitor from being changed.
A method for fabricating a capacitor of a related art semiconductor device will be explained with reference to the accompanying drawings. FIG. 1A to FIG. 1J are cross-sectional views illustrating manufacturing process steps of a capacitor of a related art semiconductor device.
Referring to FIG. 1A, a field oxide layer 2 is formed on a semiconductor substrate 1 so as to define an active region, and gates 3 are formed on the semiconductor substrate 1. Then, source and drain 4 are formed at both sides of each gate 3 in the semiconductor substrate 1, and gate sidewalls 5 are formed at both sides of each gate 3 on the semiconductor substrate 1. After forming a bit line 6 being electrically connected with the source and drain 4, a first Inter Layer Dielectric (ILD) layer 7 is formed on an entire surface of the semiconductor substrate 1, and is selectively removed so as to expose the source and drain 4 in a cell region, thereby defining a contact hole 8.
As shown in FIG. 1B, a first doped polysilicon layer 9 is deposited on the first ILD layer 7 having the contact hole 2, and Phosphorous Silicate Glass (PSG) is deposited on the first doped polysilicon layer 9. Subsequently, a photoresist layer is deposited on the entire surface of the semiconductor substrate 1, and a photoresist pattern 11 defining a capacitor region is formed in a process of selectively exposing and developing the photoresist layer. A dry-etch process is performed on the semiconductor substrate 1 using the photoresist pattern 11 as a mask, thereby forming a first doped polysilicon pattern 9a and a PSG pattern 10a, as shown in FIG. 1C. At this time, the first doped polysilicon pattern 9a serves as a bottom of a capacitor lower electrode.
Referring to FIG. 1D, a second doped polysilicon layer 12 is deposited on the entire surface of the semiconductor substrate 1. After that, as shown in FIG. 1E, the dry-etch process is performed to the second doped polysilicon layer 12, so that a second doped polysilicon pattern 12a is formed. At this time, the second doped polysilicon pattern 12a serves as a sidewall of the capacitor lower electrode, and the first doped polysilicon pattern 9a and the second doped polysilicon patter 12a serve as the capacitor lower electrode.
As shown in FIG. 1F, the PSG pattern 10a is removed in a wet-etch process so as to open the capacitor lower electrode 9a and 12a. Next, a capacitor dielectric layer 13 having an Oxide-Nitride-Oxide (ONO) structure is formed on surfaces of the exposed capacitor lower electrode 9a and 12a, as shown in FIG. 1G. In the capacitor dielectric layer 13 having the ONO structure, a native oxide layer, a nitride layer and an oxide layer are sequentially deposited on the surfaces of the capacitor lower electrode 9a and 12a. Then, a third doped polysilicon layer 14 is deposited on the semiconductor substrate 1 so as to form a capacitor upper electrode. The photoresist layer is deposited on the entire surface of the semiconductor substrate 1, and then is selectively removed, so that the photoresist layer remains only on the capacitor region, thereby forming a photoresist pattern 15. The exposed third doped polysilicon layer 14 is selectively etched by using the photoresist pattern 15 as the mask.
After removing the photoresist pattern 15 in FIG. 1H, a second ILD layer 16 is deposited on the entire surface of the semiconductor substrate 1, and then is flattened. Subsequently, contact holes 17a and 17b for forming inner lines are formed so as to expose a predetermined portion of the third doped polysilicon layer 14 as the capacitor upper electrode, and predetermined portions of the semiconductor substrate 1 on a peri-region. Referring to FIG. 1I, the contact holes 17a and 17b for forming inner lines are buried with plug metal, thereby forming plugs 18a and 18b for inner lines. Then, metal lines 19 are formed on the plugs 18a and 18b for inner lines, as shown in FIG. 1J.
However, the related art method for fabricating the capacitor of the semiconductor device has the following disadvantages.
During manufacturing the capacitor of the semiconductor device, defects may occur to the logic circuit (transistor, capacitor) due to complicated manufacturing process steps. To overcome this problem, it is required to form a repair circuit, so that a size of a chip increases.
Also, when the contact holes 17a and 17b are formed so as to form the plugs 18a and 18b for inner lines, a total thickness of the first and second ILD layers has to be 2000 xc3x85 or more, and each contact holes has to have different thickness, thereby complicating the dry-etch process and the burying process of the plug metal. Accordingly, a contact resistance of the plug increases.
Furthermore, the process for oxidizing the nitride layer is maintained so as to form the capacitor dielectric layer having the ONO structure at a high temperature, so that characteristic of the transistor and capacitor may be changed due to the high temperature.
Accordingly, the present invention is directed to a method for fabricating a semiconductor device that substantially obviates one or more problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a method for fabricating a capacitor of a semiconductor device, in which it is possible to obtain reliability in an etch process, and to simplify manufacturing process steps.
Another object of the present invention is to provide a method for fabricating a capacitor of a semiconductor device, in which the capacitor of the semiconductor device is manufactured at a lower temperature, so that it is possible to prevent electrical characteristics of the semiconductor device from being changed due to a high temperature during manufacturing process steps.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these objects and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, a method for fabricating a capacitor of a semiconductor device includes (a) forming plugs in an insulating layer for flattening so as to be in contact with a semiconductor, on which a cell region and a peri-region are defined; (b) forming a material layer for a lower electrode on the insulating layer; (c) forming a dual mask on the material layer for the lower electrode, the dual mask having a first photoresist pattern defining a bottom of the lower electrode, and a second photoresist pattern defining a side part of the lower electrode; (d) forming capacitor lower electrodes in the same shape as the dual mask in the cell region; (e) forming a capacitor dielectric layer on the surface of the capacitor lower electrode; and (f) forming a material layer for an upper electrode on an entire surface, and selectively patterning the material layer so as to form a capacitor upper electrode and metal lines simultaneously.
Preferably, the plugs are classified into plugs connecting the capacitor lower electrodes to the semiconductor substrate of the cell region, and plugs connecting the metal lines to the semiconductor substrate of the peri-region.
Preferably, the material layer for the lower electrode is made of aluminum at a thickness between 3300 xc3x85 and 3600 xc3x85. Also, the material layer for the lower electrode is formed at a temperature between 380xc2x0 C. and 410xc2x0 C.
Preferably, forming the dual mask includes forming first photoresist patterns on the plugs of the cell region, performing a hard bake process to the first photoresist patterns, and forming second photoresist patterns at the edges of the first photoresist patterns.
Preferably, the first photoresist patterns are formed at a thickness between 1900 xc3x85 and 2100 xc3x85, and the second photoresist patterns are formed at a thickness between 7900 xc3x85 and 8100 xc3x85.
Preferably, the capacitor dielectric layer is made of Al2O3 on the surface of the capacitor lower electrodes at an atmosphere of O3 by an annealing process.
Preferably, the material layer for the capacitor upper electrode is formed by sequentially depositing Al/Ti/TiN, the capacitor upper electrode is formed on the cell region having the capacitor dielectric layer, and the metal lines are formed on the plugs of the peri-region.
In another aspect of the present invention, a method for fabricating a capacitor of a semiconductor device includes (a) forming source and drain in a semiconductor substrate, on which a cell region and a peri-region are defined; (b) forming a first insulating layer for flattening on the semiconductor substrate; (c) forming first lower plugs in the first insulating layer so as to be in contact with the source and drain in the cell region, and second lower plugs in the first insulating layer so as to be in contact with the source and drain in the peri-region; (d) forming a material layer for a lower electrode on the first insulating layer; (e) forming a cylinder shaped dual mask on the material layer for the lower electrode; (f) forming capacitor lower electrodes being in contact with the first lower plugs, and having the same shape as that of the dual mask; (g) forming a capacitor dielectric layer on the surfaces of the capacitor lower electrodes; (h) forming a capacitor upper electrode on a cell region of the capacitor dielectric layer, and metal lines for being in contact with the second lower plugs; (i) forming a second insulating layer for flattening on an entire surface; and (j) forming a first upper plug being in contact with the capacitor upper electrode in the second insulating layer for flattening, and second upper plugs being in contact with the metal lines in the second insulating layer.
Preferably, forming the dual mask includes forming first photoresist patterns on the first lower plugs so as to be formed as a bottom of a cylinder shape; performing a hard bake process to the first photoresist patterns; and forming second photoresist patterns on the edges of the first photoresist patterns so as to be formed as a side part of the cylinder shape.
Preferably, the material layer for the lower electrode is made of aluminum at a thickness between 3300 xc3x85 and 3600 xc3x85.
It is to be understood that both the foregoing general description and the following detailed description of the present invention are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.